As circuit geometries continue to scale toward smaller feature sizes, interconnect delay has become a significant contributor to circuit latency. In order to reduce power consumption and increase bandwidth (and facilitate higher clock rates), three-dimensional (3D) integration utilizing die stacking with vertical through-silicon via (TSV) interconnects is being advocated. These 3D circuits replace long horizontal interconnects with shorter vertical TSVs in order to reduce latency. In this manner critical circuit paths can be partitioned across two or more dies in a stack, replacing traditional high-delay 2D interconnects with low-delay TSV vertical interconnects.
As part of the fabrication process, 3D ICs are tested before bonding (pre-bond) and after bonding (post-bond) to ensure stack yield. Pre-bond testing is performed to ensure that only known good die (KGD) are bonded together to form a stack. Post-bond testing is performed to ensure the functionality of the complete stack and screen for defects introduced in alignment and bonding.
To perform KGD testing, design-for-testability (DfT) features, such as boundary registers, built-in-self-test (BIST) architectures, or other methods may be used. Often, these DfT features include elements located on functional paths, including paths with TSVs. Although the elements on the functional paths are used to facilitate KGD determination, this placement creates an increased load and delay, which can have a negative impact on functional timing, or latency, for inter-die paths.